1. Field of the Invention
The present invention relates to a comparator, and more particularly to a high-speed and high-precision comparator for use in a high-speed analog-to-digital (A/D) converter or the like for comparing two small-amplitude signals with each other at a high speed to output a digital value corresponding to the relationship in magnitude of both signals.
2. Description of the Background Art
A type of comparator for use in an A/D converter or the like is known which includes an amplifier functioning as a preamplifier, and a latch circuit for outputting a digital value in synchronization with a clock signal. That sort of comparator is disclosed in, for example, Japanese patent laid-open publication No. 67950/1993 and U.S. Pat. No. 6,940,316 to Wakamatsu et al.
With reference first to FIG. 5, an example of such a conventional comparator includes a differential amplifier having N type metal-oxide semiconductor (NMOS) transistors M1 and M2 and a current mirror load circuit, and a latch circuit having two inversion amplifiers, or invertors, interconnected to the amplifier. In the differential amplifier having the current mirror load circuit, the transistors M1 and M2 have the source electrode thereof interconnected in common to a constant current source I1. The latch circuit configured by the two inversion amplifiers has an NMOS transistor M9 interconnected across output terminals OUTP and OUTN, and the transistor M9 has its gate electrode to which a clock signal CLK is applied.
In operation, when the clock signal CLK is at its high level, an input signal is not differentially amplified. When the clock signal CLK transits to its low level, the latch circuit configured by two inversion amplifiers is operated, or rendered active, a difference in voltage between the output terminals OUTP and OUTN which was small heretofore is in turn amplified by the differential amplifier having the current mirror load circuit to abruptly increase, and the voltages thus amplified is held on the output terminals OUTP and OUTN, as seen from FIG. 6.
In the above-described comparator, when the latch circuit is activated and latches data, it is not necessary to render the differential amplifier conducting current to hold the data inputted on input terminals INP and INN therein. However, the conventional comparator is adapted to operate the differential amplifier even when the latch circuit is activated. Thus, current flows from a supply voltage VDD to a ground, so that the current is consumed significantly, which has been problematic.